Download Accelerating Test, Validation and Debug of High Speed Serial by Yongquan Fan PDF

By Yongquan Fan

High-Speed Serial Interface (HSSI) units became common in communications, from the embedded to high-performance computing platforms, and from on-chip to a large haul. trying out of HSSIs has been a hard subject as a result of sign integrity concerns, lengthy attempt time and the necessity of pricey tools. Accelerating try, Validation and Debug of excessive velocity Serial Interfaces presents cutting edge try out and debug techniques and distinctive directions on the right way to arrive to sensible try of recent high-speed interfaces.

Accelerating attempt, Validation and Debug of excessive velocity Serial Interfaces first proposes a brand new set of rules that allows us to accomplish receiver try greater than one thousand instances swifter. Then an under-sampling established transmitter attempt scheme is gifted. The scheme can appropriately extract the transmitter jitter and end the entire transmitter try inside 100ms, whereas the attempt often takes seconds. The publication additionally offers and exterior loopback-based trying out scheme, the place and FPGA-based BER tester and a unique jitter injection method are proposed. those schemes should be utilized to validate, try out and debug HSSIs with facts price as much as 12.5Gbps at a reduce try fee than natural ATE recommendations. additionally, the ebook introduces an efficieng scheme to enforce excessive functionality Gaussian noise turbines, compatible for comparing BER functionality less than noise conditions.

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By Yongquan Fan

High-Speed Serial Interface (HSSI) units became common in communications, from the embedded to high-performance computing platforms, and from on-chip to a large haul. trying out of HSSIs has been a hard subject as a result of sign integrity concerns, lengthy attempt time and the necessity of pricey tools. Accelerating try, Validation and Debug of excessive velocity Serial Interfaces presents cutting edge try out and debug techniques and distinctive directions on the right way to arrive to sensible try of recent high-speed interfaces.

Accelerating attempt, Validation and Debug of excessive velocity Serial Interfaces first proposes a brand new set of rules that allows us to accomplish receiver try greater than one thousand instances swifter. Then an under-sampling established transmitter attempt scheme is gifted. The scheme can appropriately extract the transmitter jitter and end the entire transmitter try inside 100ms, whereas the attempt often takes seconds. The publication additionally offers and exterior loopback-based trying out scheme, the place and FPGA-based BER tester and a unique jitter injection method are proposed. those schemes should be utilized to validate, try out and debug HSSIs with facts price as much as 12.5Gbps at a reduce try fee than natural ATE recommendations. additionally, the ebook introduces an efficieng scheme to enforce excessive functionality Gaussian noise turbines, compatible for comparing BER functionality less than noise conditions.

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Additional resources for Accelerating Test, Validation and Debug of High Speed Serial Interfaces

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Figure 2-13 shows the structure of a binary matched filter receiver [38], [45]. We next introduce the “one or zero” decision principle and set the stage to evaluate the BER performance of the binary matched filter receiver. ∫ T 0 dt s1 (t ) ∑ ∫ T 0 dt s0 (t ) Fig. 2-13. Binary matched filter receiver The receiver consists of two filters, one matching to S0 (t) and the other matching to S1 (t). Each filter consists of a multiplier and an integrator. The receiver compares the output of the two filters.

Therefore, the receiver always works at the crossing point of the bathtub curve. The BER of a receiver is associated with the jitter in its input signal. As shown in Figure 3-10, with the increase of the jitter in the input signal, the bathtub curve moves up, indicating a higher BER. What we get is a series of crossed curves, as shown in Figure 3-8. Therefore, a new extrapolation algorithm needs to be developed for the jitter tolerance test. Fig. 3-10. Receiver BER scan Another significant difference is that in the receiver BER scan we have the control over the jitter PDF of the test signal, while on the other hand, we do not have 50 3 Accelerating Receiver Jitter Tolerance Testing on ATE that level of control over the jitter PDF in the transmitter.

Jitter PDFs for curve fitting In this chapter, we propose to inject the sinusoidal PJ using an AWG available on ATE. We can generate controllable amounts of PJ with only one piece of equipment – AWG. In the receiver BER scan for jitter tolerance testing, the AWG output is directly connected to the input of the receiver as shown in Figure 3-12. By varying the amount of injected PJ, we can get different BER data points. 2 Jitter Test Signal Generation 51 Fig. 3-12. Test setup for jitter tolerance testing The test setup of the proposed solution is very simple.

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