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Extra info for Analysis and Design of Analog Integrated Circuits
This behavior is illustrated in Fig. 25, which is a typical plot of fT versus Ic for an integrated-circuit npn transistor. 4 Small-Signal Models of Bi~olarTransistors 37 fr GHz f~ versus Ic for an npn integrated-circuit transistor with 6 p,m2 emitter area in a high-speed process. 25 Typical curve of currents. 5. 25 mA and 9 with Ic = 1 mA. Assuming that high-level injection effects are negligible, calculate C j , and TF, assuming both are constant. 25 rnA 1 mA Corresponding values of 77. 25 mA.
For PMOS devices, all polarities of voltages and currents are reversed. The results derived above can be used to form a large-signaI model of the NMOS transistor in saturation. The model topology is shown in Fig. 157) in saturation, ignoring the effect of channel-length modulation. 157) to find the drain current in saturation. 2 Comparison of Operating Regions of Bipolar and MOS Transistors Notice that the meaning of the word saturation for MOS transistors is quite different than for bipolar transistors.
However, technological limitations in the fabrication of transistors give rise to a number of parasitic elements that must be added to the equivalent circuit for most integrated-circuit transistors. A cross section of a typical npn transistor in a junctionisolated process is shown in Fig. 19. The means of fabricating such devices is described in Chapter 2. 2, all pn junctions have a voltage-dependent capacitance associated with the depletion region. In the cross section of Fig. 19, three depletion-region capacitances can be identified.